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IP-to-SoC prototyping demands consistency
Porting your IP to the FPGA-based prototype of an SoC design is hazardous. Particularly for new blocks, the process often involves some form of translation that can introduce errors. Sometimes, the...
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Keeping high-speed designs clean with ERC
Designers must confront faster clock speeds and driver edge rates, increasing net densities and a growing number of constrained nets. There are numerous challenges to ensuring a ‘clean design’. They...
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Mixed-signal verification of advanced SoCs using VCS AMS
The complexity of mixed-signal system-on-chip (SoC) designs is rapidly increasing due to growing analog content, advanced analog and digital interfaces and tougher requirements for safety and...
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How new RTL floorplanning techniques speed physical design
RTL floorplanning is one of the most important steps in the design flow. It is key to achieving better quality of results and faster turn-around-time. A new generation of physical RTL synthesis and...
View ArticleDVCon中国将于4月在上海亮相
To read this article in English, please click here. 首届中国ASIC设计与验证大会(DVCon 中国)将于4月19日在上海张江博雅酒店举办。会议属于Accellera的设计和验证会议系列，此前亦在美国、欧洲和印度举办。DVCon中国的目标是探讨集成电路和电子系统设计与验证中的标准语言、工具与方法学，促进中国的电子设计自动化（EDA）和IP标准化。...
View ArticleDVCon China launches this April in Shanghai
阅读本文中文版，点击这里. The first DVCon China will take place on April 19th at the Zhang Jiang Parkyard Hotel in Shanghai. The event joins Accellera’s existing editions of its series of design and verification...
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High-level synthesis for AI: Part Two
Part One of this series looked at how high-level synthesis can be used on AI-led design projects, with particular reference to computer vision. This second part discusses how to use HLS with reference...
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How to achieve accurate reset domain crossing verification
SoCs contain highly complex reset distributions and synchronization circuitry. A typical SoC today contains multiple asynchronous reset domains, making reset domain crossing (RDC) verification a...
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Machine learning overcomes library challenges at the latest process nodes
Advanced process nodes below 16nm/12nm and other specialized process technologies offer significant advantages in power, performance and area (PPA) for leading-edge SoC/IC designs. Depending on product...
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Executable specifications boost SoC and IP efficiency
Inadequate specification methods are a significant reason why today’s chips are so hard to develop. The solution is to write as many executable specifications as possible in unambiguous formats and to...
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