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ARM and the man

When microprocessor core developer ARM started in a barn outside Cambridge, England, just over fifteen years ago, odds were against it making a global impact. The team of “12 engineers and me”, as then...

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OVM testbench API for accelerating coverage closure

FPGA intellectual property (IP) is markedly different in how it needs to be verified and tested from other types. It is inherent that programmable devices will have no one use-case, although reference...

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Planning reset strategies: flow and functionality in OVM verification components

A good reset strategy has long been a part of any design methodology, playing a vital role in its success. Reset represents a fundamental property in a protocol or system; it is the first step in the...

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The new semiconductor ecosystem: wants and needs

We are now seeing the new semiconductor ecosystem rapidly taking shape. My EDA clients have been asking me what is going to be hot at DAC. Unfortunately the questions I am being asked by my...

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IJTAG: delivering an industry platform for IP test and integration

Integrating and testing IP blocks in large SoCs is typically a time consuming, manual effort. The IEEE proposed standard P1687 (‘IJTAG’) aims to solve this problem. IJTAG lets IP providers and SoC...

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IP-to-SoC prototyping demands consistency

Porting your IP to the FPGA-based prototype of an SoC design is hazardous. Particularly for new blocks, the process often involves some form of translation that can introduce errors. Sometimes, the...

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Keeping high-speed designs clean with ERC

Designers must confront faster clock speeds and driver edge rates, increasing net densities and a growing number of constrained nets. There are numerous challenges to ensuring a ‘clean design’. They...

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Mixed-signal verification of advanced SoCs using VCS AMS

The complexity of mixed-signal system-on-chip (SoC) designs is rapidly increasing due to growing analog content, advanced analog and digital interfaces and tougher requirements for safety and...

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How new RTL floorplanning techniques speed physical design

RTL floorplanning is one of the most important steps in the design flow. It is key to achieving better quality of results and faster turn-around-time. A new generation of physical RTL synthesis and...

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DVCon中国将于4月在上海亮相

To read this article in English, please click here. 首届中国ASIC设计与验证大会(DVCon 中国)将于4月19日在上海张江博雅酒店举办。会议属于Accellera的设计和验证会议系列,此前亦在美国、欧洲和印度举办。DVCon中国的目标是探讨集成电路和电子系统设计与验证中的标准语言、工具与方法学,促进中国的电子设计自动化(EDA)和IP标准化。...

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DVCon China launches this April in Shanghai

阅读本文中文版,点击这里. The first DVCon China will take place on April 19th at the Zhang Jiang Parkyard Hotel in Shanghai. The event joins Accellera's existing editions of its series of design and verification...

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Clik here to view.

The new semiconductor ecosystem: wants and needs

We are now seeing the new semiconductor ecosystem rapidly taking shape. My EDA clients have been asking me what is going to be hot at DAC. Unfortunately the questions I am being asked by my...

View Article

Image may be NSFW.
Clik here to view.

IJTAG: delivering an industry platform for IP test and integration

Integrating and testing IP blocks in large SoCs is typically a time consuming, manual effort. The IEEE proposed standard P1687 (‘IJTAG’) aims to solve this problem. IJTAG lets IP providers and SoC...

View Article


Image may be NSFW.
Clik here to view.

IP-to-SoC prototyping demands consistency

Porting your IP to the FPGA-based prototype of an SoC design is hazardous. Particularly for new blocks, the process often involves some form of translation that can introduce errors. Sometimes, the...

View Article

Image may be NSFW.
Clik here to view.

Keeping high-speed designs clean with ERC

Designers must confront faster clock speeds and driver edge rates, increasing net densities and a growing number of constrained nets. There are numerous challenges to ensuring a ‘clean design’. They...

View Article


Image may be NSFW.
Clik here to view.

Mixed-signal verification of advanced SoCs using VCS AMS

The complexity of mixed-signal system-on-chip (SoC) designs is rapidly increasing due to growing analog content, advanced analog and digital interfaces and tougher requirements for safety and...

View Article

Image may be NSFW.
Clik here to view.

How new RTL floorplanning techniques speed physical design

RTL floorplanning is one of the most important steps in the design flow. It is key to achieving better quality of results and faster turn-around-time. A new generation of physical RTL synthesis and...

View Article


DVCon中国将于4月在上海亮相

To read this article in English, please click here. 首届中国ASIC设计与验证大会(DVCon 中国)将于4月19日在上海张江博雅酒店举办。会议属于Accellera的设计和验证会议系列,此前亦在美国、欧洲和印度举办。DVCon中国的目标是探讨集成电路和电子系统设计与验证中的标准语言、工具与方法学,促进中国的电子设计自动化(EDA)和IP标准化。...

View Article

DVCon China launches this April in Shanghai

阅读本文中文版,点击这里. The first DVCon China will take place on April 19th at the Zhang Jiang Parkyard Hotel in Shanghai. The event joins Accellera’s existing editions of its series of design and verification...

View Article

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Clik here to view.

High-level synthesis for AI: Part Two

Part One of this series looked at how high-level synthesis can be used on AI-led design projects, with particular reference to computer vision. This second part discusses how to use HLS with reference...

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